1. Field
Exemplary embodiments of the present invention relate to a memory device, an operation method thereof, and more particularly, to a repair technology.
2. Description of the Related Art
FIG. 1 is a diagram explaining a repair operation in a conventional memory device (for example, a DRAM).
A memory device may include a plurality of memory banks and one of the memory banks is shown in FIG. 1. Referring to FIG. 1, the memory device includes a memory array 110 which includes a plurality of memory cells, a row circuit 120 for activating a word line selected by a row address R_ADD, and a column circuit 130 for accessing (reading or writing) data DATA of a bit line selected by a column address C_ADD.
A row fuse circuit 140 stores a row address corresponding to a defective memory cell in the memory array 110, as a repair row address REPAIR_R_ADD. A row comparison unit 150 compares the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 and the row address R_ADD inputted from an exterior of the memory device. If the repair row address REPAIR_R_ADD and the row address R_ADD correspond to each other, the row comparison unit 150 controls the row circuit 120 to activate a redundancy word line instead of a word line designated by the row address R_ADD. That is to say, a row (word line) corresponding to the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 is replaced with a redundancy row (word line).
In the drawing, the reference symbol RACT represents a signal which is activated in response to an active command for commanding the activation of a word line in the memory array 110 and deactivated in response to a precharge command for commanding the deactivation of a word line in the memory array 110. Also, the reference symbol IRD represents a read command, and the reference symbol IWT represents a write command.
In the conventional row fuse circuit 140, laser fuses are generally included and used. Laser fuses store high or low logic level of data depending on whether the laser fuses are cut or not. Although laser fuses may be programmed in a wafer level of a memory device, it is not possible to program the laser fuses after a wafer is mounted in a package. Also, it is difficult to design the laser fuses smaller than a certain size because of limitations in decreasing the pitch length thereof.
In order to overcome such issues, a nonvolatile memory such as an E-fuse array circuit, a NAND flash memory a NOR flash memory, an MRAM (magnetoresistive random access memory), an STT-MRAM (spin transfer torque magnetoresistive random access memory), a ReRAM (resistive random access memory) and a PC RAM (phase change random access memory) as disclosed in U.S. Pat. Nos. 6,940,751, 6,777,757, 6,667,902, 7,173,851 and 7,269,047 is included in a memory device, and repair information (repair addresses) is stored in the nonvolatile memory, for use.
FIG. 2 is a diagram showing the use of a nonvolatile memory circuit to store repair information in a memory device.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, registers 210_0 to 210_3 which are provided in the respective memory banks BK0 to BK3 to store repair information, and a nonvolatile memory circuit 201.
The nonvolatile memory circuit 201 is a substitution circuit for the row fuse circuit 140 shown in FIG. 1. Repair information, that is, repair addresses, corresponding to all the banks BK0 to BK3 is stored in the nonvolatile memory circuit 201. The nonvolatile memory circuit 201 may be any one of nonvolatile memories such as an E-fuse array circuit, a NAND flash memory, a NOR flash memory, an MRAM (magnetoresistive random access memory), an STT-MRAM (spin transfer torque magnetoresistive random access memory), a ReRAM (resistive random access memory) and a PC RAM (phase change random access memory).
The registers 210_0 to 210_3 are provided in the respective memory banks BK0 to BK3 and store repair information of the respective memory banks BK0 to BK3. The register 210_0 stores the repair information of the memory bank BK0, and the register 210_2 stores the repair information of the memory bank BK2. The registers 210_0 to 210_3 may include latch circuits, and may store the repair information only while power is supplied. The repair information to be stored in the registers 210_0 to 210_3 is transmitted from the nonvolatile memory circuit 201.
The repair information stored in the nonvolatile memory circuit 201 is transmitted to and stored in the registers 210_0 to 210_3 to be used for a repair operation. Since the nonvolatile memory circuit 201 is configured in an array, a predetermined time is required to call the data stored in the nonvolatile memory circuit 201. Because the memory device cannot make an immediate call for the data stored in the nonvolatile memory circuit 201, it is impossible to perform a repair operation by directly using the data stored in the nonvolatile memory circuit 201. Therefore, a boot-up operation, in which the repair information stored in the nonvolatile memory circuit 201 is transmitted to and stored in the registers 210_0 to 210_3, is performed, and a repair operation is performed using the repair information stored in the registers 210_0 to 210_3, after the boot-up operation is performed.
As the row fuse circuit 140 configured by laser fuses replaced with the nonvolatile memory circuit 201 and the registers 210_0 to 210_3 it is possible to repair an additional defect which occurs in a wafer and next level of a memory device. Meanwhile, research has been made for a technology capable of repairing a defect occurring after the fabrication of a semiconductor memory device by accessing the nonvolatile memory circuit 201 even after the fabrication of the semiconductor memory device (for example, after the sale of a product).